AMD "Fiji" Block Diagram Revealed, Runs Cool and Quiet

AMD's upcoming flagship GPU silicon, codenamed "Fiji," which is breaking ground on new technologies, such as HBM, memory-on-package, a specialized substrate layer that connects the GPU with it, called Interposer; features a hefty feature-set. More on the "Fiji" package and its memory implementation, in our older article. Its block diagram (manufacturer-drawn graphic showing the GPU's component hierarchy), reveals a scaling up, of the company's high-end GPU launches over the past few years.

"Fiji" retains the quad Shader Engine layout of "Hawaii," but packs 16 GCN Compute Units (CUs), per Shader Engine (compared to 11 CUs per engine on Hawaii). This works out to a stream processor count of 4,096. Fiji is expected to feature a newer version of the Graphics CoreNext architecture than "Hawaii." The TMU count is proportionately increased, to 256 (compared to 176 on "Hawaii"). AMD doesn't appear to have increased the ROP count, which is still at 64. The most significant change, however, is its 4096-bit HBM memory interface, compared to 512-bit GDDR5 on "Hawaii."

Read full story

http://ift.tt/1I9KSas